Open-Collector as Selector

We use the open-collector configuration to make five digital switches like figure below. The range of incoming pulse is 1 Hz to 99 MHz. By adding the 74HC393 frequency divider, we get the output that its frequency range is 1 Hz to 900 kHz. This is done because the frequency range for incoming pulse that can feed to timer 0 of microcontroller is 920 kHz.
We have three states. Each state has its frequency range.
1. High Frequency State.
This state sets HFPin, so the incoming pulse (f) can feed to CP1 (Clock Pulse of counter 1). This state also sets HFPin1, so the output frequency of counter 0 feed to CP0 (Clock Pulse of counter 0). The incoming pulse was isolated to CP0 by resetting MFPin. Next the output frequency of counter 0 was emitted from Q2-0 to timer 0. To do this, we set HMFPin and reset LFPin.
2. Medium Frequency State.
This state resets HFPin and sets MFPin, so incoming pulse feed to CP0 . The 3-bit counter/divider works and emits the pulse at Q2-0.
3. Low Frequency State.
This state sets the LFPin and resets the others. The incoming pulse feed through to timer 0.
The schematic diagram is the same as the schematic diagram of dual channel 920 kHz Frequency Counter project, but before counter 0 pin (P3.4), we must add this divider.

Auto-select Subroutine Program
When counting the incoming pulse (by timer 0) was running, counter/divider that was activated must proper with the incoming frequency. To do this, the Auto-select Subroutine Program will be run before the counting process. This subroutine will determine the counter/divider that must be activated.
This subroutine works as follow.
1. Check if incoming pulse is high frequency.

• Activate HF state: set HFPin, HFPin1, HMFPin; and reset MFPin, LFPin (See table bellow). This will enable output of the 3-bit and 4-bit counter/divider.
• Count incoming pulse during 20 ms intervals.
• If result is grater than 56,250, the incoming pulse must be high frequency, go to step 4.

2. Check if incoming pulse is medium frequency.

• Activate MF state: set MFPin, HMFPin; and reset HFPin, HFPin1, LFPin. This will enable output of the 3-bit counter/divider but disable the other.
• Count incoming pulse during 20 ms intervals.
• If result is grater than 112,500, the incoming pulse must be medium frequency. So, and go to step 4.

3. Activate LF state: set LFPin and reset the others. This will disable all output of all counter/divider.
4. Count incoming pulse during 1 s intervals.

aaaaaHFPin HFPin1 MFPin HMFPin LFPin
aaaaaP0.1 aa P0.2 aaP0.3 aa P0.4 aaP0.5
HF aaaaa1 aaaaa 1 aaaaa0 aaaaa1 aaaaa0
MF aaaaa0 aaaaa 0 aaaaa1 aaaaa1 aaaaa0
LF aaaaaa0 aaaaa0 aaaaa0 aaaaa0 aaaaa1

To do four step above we make some subroutine: PreDelay20ms to prepare timer 2 for delay 20 ms, PreCount20msT0 to count the incoming pulse of timer 0 during 20 ms intervals, CheckIfHF to check if incoming pulse is high frequency, CheckIfMF to check if incoming pulse is medium frequency, CountF to count incoming frequency during 1 s interval, CountHFFrequency to divide the incoming high frequency by 128 and prepare it for display, CountMFFrequency to divide the incoming medium frequency by eight and prepare it for display.
The listing program can be downloaded here.